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STRUCTURE NAME OF PRODUCT
Silicon Monolithic Integrated Circuit DC-AC Inverter Control IC
TYPE
4ch control with Push-Pull Short circuit protection with Timer Latch Sequencing easily achieved with Soft Start Control Under Voltage Lock Out Short circuit protection with over voltage Mode-selectable the operating or stand-by mode by stand-by pin Synchronous operating the other BD9892FV IC's BURST mode controlled by PWN and DC input Output linear control by external DC voltage
FUNCTION
Absolute Maximum RatingsTa = 25
Parameter Supply Voltage Operating Temperature Range Storage Temperature Range Power Dissipation Maximum Junction Temperature
*
Symbol VCC Topr Tstg Pd Tjmax
Limits 15 -40+90 -55+125 1062* +150
Unit V mW
Pd derated at 8.5mW/ for temperature above Ta = 25 (When mounted on a PCB 70.0mmx70.0mmx1.6mm)
Operating condition
Parameter Supply voltage CT oscillation frequency BCT oscillation frequency Symbol VCC fCT fBCT Limits 5.514.0 20150 0.050.50 Unit V kHz kHz
Status of this document The Japanese version of this document is the official specification. Please use the translation version of this document as a reference to expedite understanding of the official version. If these are any uncertainty in translation version of this document, official version takes priority.
REV. B
2/4 Electric CharacteristicsTa=25VCC=7V
Parameter WHOLE DEVICE Operating current Stand-by current OVER VOLTAGE DETECT FB over voltage detect voltage STAND BY CONTROL Stand-by voltage H Stand-by voltage L TIMER LATCH Timer Latch voltage Timer Latch current BURST MODE BOSC Max voltage BOSC Min Voltage BOSC constant current BOSC constant current OSC BLOCK OSC constant current OSC Max voltage OSC Min voltage MAX DUTY Soft start current IS COMP detect Voltage SS COMP detect voltage SRT ON resistance UVLO BLOCK Operating voltage Hysteresis width Operating voltage (External UVLO) Hysteresis width FB OVP Mask Threshold voltage REG BLOCK REG output voltage REG source current FEED BACK BLOCK IS threshold voltage VS threshold voltage IS source current 1 IS source current 2 VS source current OUTPUT BLOCK NAch output voltage NBch output voltage NAch output voltage NBch output voltage Symbol Icc1 Icc2 Vovf VstH VstL Vcp Icp MIN. 2.20 2.0 -0.3 1.9 0.5 Limits TYP. 15.0 2 2.40 2.0 1.0 MAX. 23.0 10 2.60 VCC 0.8 2.1 1.5 Unit mA A V V V V A fBCT=0.2kHz BCT(A,B)common spec fBCT=0.2kHz BCT(A,B) common spec BCT(A,B) common spec BRT=36k BCT=0.048F BCT(A,B) common spec System System CT=0.5V Conditions
VburH VburL IBCT fBCT ICT VoscH VoscL MAXDUTY Iss Visc Vss RSRT V_A_uvloH V_A_uvlo Vuvlo2 Vuvlo2 Vuvlo_fb VREG IREG Vis Vvs Iis1 Iis2 Ivs H H L L VoutNAH VoutNBH VoutNAL VoutNBL RsinkNA RsourceNA RsinkNB RsourceNB fOUT
1.94 0.4 1.35/BRT 292.5 1.35/RT 1.8 0.3 44 1.0 0.45 2.0 4.95 0.21 2.242 0.083 2.222 3.038 5.0 1.225 1.220 13.0 VCC-0.3 VCC-0.3 58.5
2.0 0.5 1.5/BRT 300.0 1.5/RT 2.0 0.5 46.5 2.0 0.50 2.2 200 5.15 0.29 2.315 0.110 2.315 3.100 1.250 1.250 20.0 VCC-0.1 VCC-0.1 0.1 0.1 5 8 5 8 60.0
2.06 0.6 1.65/BRT 307.5 1.65/RT 2.2 0.7 49 3.0 0.55 2.4 400 5.35 0.037 2.388 0.137 2.407 3.162 1.275 1.280 1.5 27.0 1.0 0.3 0.3 10 16 10 16 61.5
V V A Hz A V V % A V V V V V V V V mA V V A A A V V V V KHz
fCT=60kHz fCT=60kHz fCT=60kHz
SS(A,B) common spec
VCC(A,B) common spec VCC(A,B) common spec
Connected REG When Vref pin is open
IS(1,2,3,4) common VS(1,2,3,4) common DUTY=2.0V IS(1,2,3,4) common DUTY=0VIS=0.5V IS(1,2,3,4) common VS(1,2,3,4) common
spec spec spec spec spec
NAch output sink resistance NAch output source resistance NBch output sink resistance NBch output source resistance Drive output frequency COMP BLOCK Over voltage detect Hysteresis width PROTECT CLOCK
NA(1,2,3,4) common spec NB(1,2,3,4) common spec NA(1,2,3,4) common spec NB(1,2,3,4) common spec Isink=10mA NA(1,2,3,4) common spec Isource=10mA NA(1,2,3,4) common spec Isink=10mA NB(1,2,3,4) common spec Isource=10mA NB(1,2,3,4) common spec RT=20kCT=420pF NA,NB(1,2,3,4) common spec COMP(A,B) common spec COMP(A,B) common spec
VCOMP VCOMP
3.033 0.07
3.100 0.1
3.167 0.13
V V V V
Normal output voltage VPH 2.9 3.1 3.3 Protect output voltage VPL 0.5 This product is not designed for normal operation with in a radio active environment.
REV. B
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Package Dimensions
Device Mark
Pin Description
Pin No. Pin Name Function
1
COMP_A NA1 NB1 PGND_A NB2 NA2 STB VCC_A VREF FAIL PH REG DUTY BRT BCT_B
Over voltage detect for 1ch,2ch FET driver for 1ch FET driver for 1ch Ground for FET drivers FET driver for 2ch FET driver for 2ch Stand-by switch Supply voltage input Reference voltage input for IS error amplifier Protect clock output Shift control input Internal regulator output Control PWM mode and BURST mode External resistor from BRT to GND for adjusting the BURST triangle oscillator External capacitor from BCT to GND for adjusting the BURST triangle oscillator for 3ch,4ch External capacitor from BCT to GND for adjusting the BURST triangle oscillator for 1ch,2ch GROUND External capacitor from CT to GND adjusting the triangle oscillator External resistor from RT to GND adjusting the triangle oscillator External resistor from SRT to RT adjusting the triangle oscillator External capacitor from CP to GND Timer Latch for 1ch,2ch External capacitor from CP to GND Timer Latch for 3ch,4ch for for for for for
BD9892K
2 3 4 5 6 7 8 9
Lot No.
10 11 12 13 14 15
QFP44 (unit:mm)
16 17 18
BCT_A GND CT RT SRT CP_A CP_B
Block Diagram
VCC_A VCC_B REG VREF CT RT BRT BCT_A BCT_B DUTY PH
19 20 21
REG BLOCK STB BLOCK
OSC BLOCK
BOSC BLOCK
DUTY BLOCK
22
STB
SYSTEMON/OFF
SS_A SS_B FB1 IS1 VS1 F/B BLOCK CT SS_A PWM BLOCK
UVLO BLOCK
VCC UVLO
23 24
VCC_A
SS_A SS_B VCC_B UVLO NA4 NB4 PGND_B NB3 NA3 COMP_B VS4 IS4 FB4 VS3 IS3 FB3 FB2 IS2 VS2 FB1 IS1 VS1
LOGIC BLOCK
OUTPUT BLOCK
NA1 NB1
FB2 IS2 VS2 F/B BLOCK SS_A CT PWM BLOCK LOGIC BLOCK
VCC_A OUTPUT BLOCK NA2 NB2
PGND_A FB3 VCC_B IS3 VS3 F/B BLOCK SS_B CT FB4 IS4 VS4 PWM BLOCK LOGIC BLOCK OUTPUT BLOCK NA3 NB3
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
External capacitor from SS to GND for Soft Start Control 1ch,2ch External capacitor from SS to GND for Soft Start Control 3ch,4ch Supply voltage input External Under Voltage Lock OUT FET driver for 4ch FET driver for 4ch Ground for FET drivers FET driver for 3ch FET driver for 3ch Over voltage detect for 3ch,4ch Error amplifier input Error Error Error Error Error Error Error Error Error Error Error amplifier amplifier amplifier amplifier amplifier amplifier amplifier amplifier amplifier amplifier amplifier input output input input output output input input output input input
VCC_B F/B BLOCK SS_B CT PGND_B PWM BLOCK LOGIC BLOCK OUTPUT BLOCK NA4 NB4
GND PROTECT BLOCK FAIL
COMP_A
COMP_B
CP_A
CP_B
SRT
REV. B
4/4
NOTE FOR USE
When designing the external circuit, including adequate margins for variation between external devices and the IC.Use adequate margins for steady state and transient characteristics. Recommended Operating Range The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended operating range. The standard electrical characteristic values cannot be guaranteed at other voltages in the operating ranges, however, the variation will be small. Mounting Failures Mounting failures, such as misdirection or miscounts, may harm the device. Electromagnetic Fields A strong electromagnetic field may cause the IC to malfunction. . The GND pin should be the location within 0.3V compared with the PGND(A,B) pin
BD9892K has the short circuit protection with Thermal Shut Down System. When STB or Vcc pin re-supplied, They enables to cancel the latch. If It rise the temperature of the chip more than 170(TYP), It make the external FET OFF Absolute maximum ratings are those values that, if exceeded, may cause the life of a device to become significantly shortened. Moreover, the exact failure mode caused by short or open is not defined. Physical countermeasures, such as a fuse, need to be considered when using a device beyond its maximum ratings. About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage is switching. Make sure to leave adequate margin for this IC variation. On operating Slow Start Control (SS(A,B) is less than 2.2V), It does not operate Timer Latch. By STB voltage, BD9892K is changed to 2 states. Therefore, do not input STB pin voltage between one state and the other state (0.82.0). The pin connected a connector need to connect to the resistor for electrical surge destruction. This IC is a monolithic IC which (as shown is Fig-1)has P+ substrate and between the various pins. A P-N junction is formed from this P layer of each pin. For example, the relation between each potential is as follows, (When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.) (When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.) Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits as well as operation faults and physical damage. Accordingly you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND(P substrate)voltage to an input pin.
Resistance (PinA) (PinB) C Transistor (NPN) B E GND P P N P substrate GND Parasitic diode N P P substrate GND Parasitic diode (PinB) (PinA) B Parasitic diode GND
N
N
C E GND
Other adjacent components
Parasitic diode
Fig.1 Simplified structure of a Bipolar IC
REV. B
Notice
Notes
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